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1 ?1999 integrated device technology, inc. december 1999 dsc-3821/03 zbt and zero bus turnaround are trademarks of integrated device technology, inc. and the architecture is supported by micron te chnology and motorola inc. pin description summary description the IDT71V546 is a 3.3v high-speed 4,718,592-bit (4.5 megabit) synchronous sram organized as 128k x 36 bits. it is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. thus it has been given the name zbt tm , or zero bus turn-around. address and control signals are applied to the sram during one features u u u u u 128k x 36 memory configuration, pipelined outputs u u u u u supports high performance system speed - 133 mhz (4.2 ns clock-to-data access) u u u u u zbt tm feature - no dead cycles between write and read cycles u u u u u internally synchronized registered outputs eliminate the need to control oe u u u u u single r/ w (read/write) control pin u u u u u positive clock-edge triggered address, data, and control signal registers for fully pipelined applications u u u u u 4-word burst capability (interleaved or linear) u u u u u individual byte write ( bw 1 - bw 4 ) control (may tie active) u u u u u three chip enables for simple depth expansion u u u u u single 3.3v power supply (5%) u u u u u packaged in a jedec standard 100-pin tqfp package clock cycle, and two cycles later its associated data cycle occurs, be it read or write. the IDT71V546 contains data i/o, address and control signal regis- ters. output enable is the only asynchronous signal and can be used to disable the outputs at any given time. a clock enable ( cen ) pin allows operation of the IDT71V546 to be suspended as long as necessary. all synchronous inputs are ignored when cen is high and the internal device registers will hold their previous values. there are three chip enable pins ( ce 1 , ce 2 , ce 2 ) that allow the user to deselect the device when desired. if any one of these three is not active when adv/ ld is low, no new memory operation can be initiated and any burst that was in progress is stopped. however, any pending data transfers (reads or writes) will be completed. the data bus will tri-state two cycles after the chip is deselected or a write initiated. the IDT71V546 has an on-chip burst counter. in the burst mode, the IDT71V546 can provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the lbo input pin. the lbo pin selects between linear and interleaved burst sequence. the adv/ ld signal is used to load a new external address (adv/ ld = low) or increment the internal burst counter (adv/ ld = high). the IDT71V546 sram utilizes idt's high-performance, high-volume 3.3v cmos process, and is packaged in a jedec standard 14mm x 20mm 100-pin thin plastic quad flatpack (tqfp) for high board density. IDT71V546 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs a 0 - a 16 address inputs input synchronous ce 1 , ce 2 , ce 2 three chip enables input synchronous oe output enable input asynchronous r/ w read/write signal input synchronous cen clock enable input synchronous bw 1 , bw 2 , bw 3 , bw 4 individual byte write selects input synchronous clk clock input n/a adv/ ld advance burst address / load new address input synchronous lbo linear / interleaved burst order input static i/o 0 - i/o 31 , i/o p1 - i/o p4 data input/output i/o synchronous v dd 3.3v power supply static v ss ground supply static 38 21 tb l 01
2 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges pin definitions (1) note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk. symbol pin function i/o active description a 0 - a 16 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk and adv/ ld low, cen low and true chip enables. adv/ ld address/load i n/a adv/ ld is a synchronous input that is used to load the internal registers with new address and control when it is sampled low at the rising edge of clock with the chip selected. when adv/ ld is low with the chip deselected, any burst in progress is terminated. when adv/ ld is sampled high then the internal burst counter is advanced for any burst that was in progress. the external addresses are ignored when adv/ ld is sampled high. r/ w read/write i n/a r/ w signal is a synchronous input that identified whether the current load cycle initiated is a read or write access to the memory array. the data bus activity for the current cycle takes place two clock cycles later. cen clock enable i low synchronous clock enable input. when cen is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged. the effect of cen sampled high on the device outputs is as if the low to high clock transition did not occur. for normal operation, cen must be sampled low at rising edge of clock. bw 1 - bw 4 individual byte write enables i low synchronous byte write enables. enable 9-bit byte has its own active low byte write enable. on load write cycles (when r/ w and adv/ ld are sampled low) the appropriate byte write signal ( bw 1 - bw 4 ) must be valid. the byte write signal must also be valid on each cycle of a burst write. byte write signals are ignored when r/ w is sampled high. the appropriate byte(s) of data are written into the device two cycles later. bw 1 - bw 4 can all be tied low if always doing write to the entire 36-bit word. ce 1 , ce 2 chip enables i low synchronous active low chip enable. ce 1 and ce 2 are used with ce 2 to enable the IDT71V546. ( ce 1 or ce 2 sampled high or ce 2 sampled low) and adv/ ld low at the rising edge of clock, initiates a deselect cycle. the zbt ? has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated. ce2 chip enable i high synchronout active high chip enable. ce 2 is used with ce 1 and ce 2 to enable the chip . ce 2 has inverted polarity but otherwise identical to ce 1 and ce 2 . clk clock i n/a this is the clock inp ut to the IDT71V546. except for oe , all timing references for the device are made with respect to the rising edge of clk. i/o 0 - i/o 31 i/o p1 - i/o p4 data input/output i/o n/a synchronous data input/output (i/o) pins. both the data input path and data output path are registered and triggered by the rising edge of clk. lbo linear burst order i low burst order selection input. when lbo is high the interleaved burst sequence is selected. when lbo is low the linear burst sequence is selected. lbo is a static dc input. oe output enable i low asynchronous output enable. oe must be low to read data from the 71v546. when oe is high the i/o pins are in a high-impedance state. oe does not need to be actively controlled for read and write cycles. in normal operation, oe can be tied low. v dd power supply n/a n/a 3.3v power supply input. v ss ground n/a n/a ground pin. 3821 tbl 02
6.42 3 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges functional block diagram recommended operating temperature and supply voltage recommended dc operating conditions clk dq dq dq address a [0:16] control logic address control di do input r egister 3821 drw 01 clock data i/o [0:31], i/o p[1:4] d q clk output register mux sel gate o e c e 1 ,ce 2 , c e 2 r/ w c e n adv/ l d b w x l b o 128k x 36 bit memory array . grade temperature v ss v dd commercial 0 o c to +70 o c0v 3.3v5% industrial -40 o c to +85 o c0v 3.3v5% 38 21 tb l 03 notes: 1. v il (min.) = C1.0v for pulse width less than t cyc/2 , once per cycle. 2. v ih (max.) = +6.0v for pulse width less than t cyc/2 , once per cycle. symbol parameter min. typ. max. unit v dd supply voltage 3.135 3.3 3.465 v v ss ground 0 0 0 v v ih input high voltage - inputs 2.0 ____ 4.6 v v ih input high voltage - i/o 2.0 ____ v dd +0.3 (2) v v il input low voltage -0.5 (1) ____ 0.8 v 38 21 tbl 04
4 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges absolute maximum ratings (1) capacitance (t a = +25c, f = 1.0mhz, tqfp package) pin configuration top view tqfp 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e 1 c e 2 b w 4 b w 3 b w 2 b w 1 c e 2 v d d v s s c lk r / w c e n o e a d v / ld n c (2) n c (2) a 8 a 9 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c n c n c n c lb o a 14 a 13 a 12 a 11 a 10 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v dd v ss i/o 29 i/o 28 i/o 27 i/o 26 v ss v dd i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v dd v ss i/o 21 i/o 20 i/o 19 i/o 18 v ss v dd i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v dd v ss i/o 13 i/o 12 i/o 11 i/o 10 v ss v dd i/o 9 i/o 8 v ss v dd i/o 7 i/o 6 v dd v ss i/o 5 i/o 4 i/o 3 i/o 2 v ss v dd i/o 1 i/o 0 pk100-1 3821 drw 02 v dd (1) i/o 15 i/o p3 v dd i/o p4 a 15 a 16 i/o p1 v dd i/o p2 v ss . . symbol rating value unit v te rm (2 ) te r m i n a l vo l ta g e with respect to gnd -0.5 to +4.6 v v te rm (3 ) te r m i n a l vo l ta g e with respect to gnd -0.5 to v dd +0.5 v t a operating temperature 0 to +70 o c t bias temperature under bias -55 to +125 o c t stg storage temperature -55 to +125 o c p t power dissipation 2.0 w i out dc output current 50 ma 3 821 tb l 05 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd and input terminals only. 3. i/o terminals. note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 5 pf c i/o i/o capacitance v out = 3dv 7 pf 3821 tbl 06 notes: 1. pin 14 does not have to be connected directly to v dd as long as the input voltage is > v ih . 2. pins 83 and 84 are reserved for future a 17 (8m) and a 18 (16m) respectively.
6.42 5 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges synchronous truth table (1) partial truth table for writes (1) notes: 1. l = v il , h = v ih , x = dont care. 2. when adv/ ld signal is sampled high, the internal burst counter is incremented. the r/ w signal is ignored when the counter is advanced. therefore the nature of the burst cycle (read or write) is determined by the status of the r/ w signal when the first address is loaded at the beginning of the burst cycle. 3. deselect cycle is initiated when either ( ce 1 , or ce 2 is sampled high or ce 2 is sampled low) and adv/ ld is sampled low at rising edge of clock. the data bus will tri-state two cycles after deselect is initiated. 4. when cen is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. the state of all th e internal registers and the i/ os remains unchanged. 5. to select the chip requires ce 1 = l, ce 2 = l, ce 2 = h on these chip enables. chip is deselected if either one of the chip enables is false. 6. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. 7. q - data read from the device, d - data written to the device. cen r/ w chip (5) enable adv/ ld bw x address used previouis cycle current cycle i/o (2 cycles later) l l select l valid external x load write d (7) l h select l x external x load read q (7) l x x h valid internal load write/ burst write burst write (advance burst counter) (2) d (7) l x x h x internal load read/ burst read burst read (advance burst counter) (2) q (7) l x deselect l x x x deselect or stop (3) hiz l x x h x x deselect / noop noop hiz hxx xxx x suspend (4) previous value 38 21 tb l 07 notes: 1. l = v il , h = v ih , x = dont care. 2. multiple bytes may be selected during the same cycle. operation r/ w bw 1 bw 2 bw 3 bw 4 read hxxxx write all bytes l l l l l write byte 1 (i/o [0:7], i/o p1 ) (2) llhhh write byte 2 (i/o [8:15], i/o p2 ) (2) lhlhh write byte 3 (i/o [16:23], i/o p3 ) (2) lhhlh write byte 4 (i/o [24:31], i/o p4 ) (2) lhhhl no write lhhhh 3821 tbl 08
6 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges functional timing diagram (1) note: 1. this assumes cen , ce 1 , ce 2 , ce 2 are all true. 2. all address, control and data_in are only required to meet set-up and hold time with respect to the rising edge of clock. dat a_out is valid after a clock-to-data delay from the rising edge of clock. a37 c37 d/q35 n+29 a29 c29 d/q27 address (a0 - a16) control (r /w, adv/ ld , bw x) data i/o [0:31], i/o p[1:4] cycle clock n+30 a30 c30 d/q28 n+31 a31 c31 d/q29 n+32 a32 c32 d/q30 n+33 a33 c33 d/q31 n+34 a34 c34 d/q32 n+35 a35 c35 d/q33 n+36 a36 c36 d/q34 (2) (2) (2) 3821 drw 03 n+37 a37 c37 d/q35 , interleaved burst sequence table ( lbo =v dd ) linear burst sequence table ( lbo =v ss ) note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address00011011 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11 10 01 00 3821 tbl 09 note: 1. upon completion of the burst sequence the counter wraps around to its initial state and continues counting. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address00011011 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1) 11 00 01 10 3821 tbl 10
6.42 7 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges device operation - showing mixed load, burst, deselect and noop cycles (2) notes: 1. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 2. h = high; l = low; x = dont care; z = high impedance. cycle address r/ w adv/ ld ce (1) cen bw x oe i/o comments n a0 h l l l x x x load read n+1 x x h x l x x x burst read n+2 a1 h l l l x l q0 load read n+3 x x l h l x l q 0+1 deselect or stop n+4 x x h xlxlq1noop n+5 a2 h l l l x x z load read n+6 x x h x l x x z burst read n+7 x x l h l x l q2 deselect or stop n+8 a3 l l l l l l q 2+1 load write n+9 x x h x l l x z burst write n+10 a4 l l l l l x d3 load write n+11 x x l h l x x d 3+1 deselect or stop n+12 x x h x l x x d4 noop n+13 a5 l l l l l x z load write n+14 a6 h l l l x x z load read n+15 a7 l l l l l x d5 load write n+16 x x h x l l l q6 burst write n+17 a8 h l l l x x d7 load read n+18 x x h x l x x d 7+1 burst read n+19 a9 l l l l l l q8 load write 3821 tbl 11
8 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges read operation (1) note: 1. h = high; l = low; x = dont care; z = high impedance.. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce2 = l. burst read operation (1) note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 h l l l x x x address and control meet setup n+1 x x x x l x x x clock setup valid n+2 x x x x x x l q0 contents of address a0 read out 38 21 tb l 12 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 h l l l x x x address and control meet setup n+1 x x h x l x x x clock setup valid, advance counter n+2 x x h x l x l q0 ad dress a0 read out, inc. count n+3 x x h xlxlq 0+1 address a 0+1 read out, inc. count n+4 x x h xlxlq 0+2 address a 0+2 read out, inc. count n+5 a1 h l l l x l q 0+3 address a 0+3 read out, load a1 n+6 x x h x l x l q0 ad dress a0 read out, inc. count n+7 x x h x l x l q1 ad dress a1 read out, inc. count n+8 a2 h l l l x l q 1+1 address a 1+1 read out, load a2 3821 tbl 13
6.42 9 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges note: 1. h = high; l = low; x = dont care; ? = dont know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. burst write operation (1) note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. write operation (1) cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x x xlxxxclock setup valid n+2 x x x x l x x d0 write to address a0 3821 tbl 14 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x h x l l x x clock setup valid, inc. count n+2 x x h x l l x d0 address a0 write, inc. count n+3 x x h x l l x d 0+1 address a 0+1 write, inc. count n+4 x x h x l l x d 0+2 address a 0+2 write, inc. count n+5 a1 l l l l l x d 0+3 address a 0+3 write, load a1 n+6 x x h x l l x d0 address a0 write, inc. count n+7 x x h x l l x d1 address a1 write, inc. count n+8 a2 l l l l l x d 1+1 address a 1+1 write, load a2 3821 tbl 15
10 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce2 = l. read operation with clock enable used (1) note: 1. h = high; l = low; x = dont care; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. write operation with clock enable used (1) cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 h l l l x x x address and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a1 h l llxxxclock valid n+3 x x x x h x l q0 clock ignored. data q0 is on the bus n+4 x x x x h x l q0 clock ignored. data q0 is on the bus n+5 a2 h l l l x l q0 a ddress a0 read out (but trans.) n+6 a3 h l l l x l q1 ad dress a1 read out (bus trans.) n+7 a4 h l l l x l q2 ad dress a2 read out (bus trans.) 38 21 tb l 16 cycle address r/ w adv/ ld ce (2) cen bw x oe i/o comments n a0 l l l l l x x address and control meet setup n+1 x x x x h x x x clock n+1 ignored n+2 a1 l l l l l x x clock valid n+3 x x x xhxxxclock ignored n+4 x x x xhxxxclock ignored n+5 a2 l l l l l x d0 write data d0 n+6 a3 l l l l l x d1 write data d1 n+7 a4 l l l l l x d2 write data d2 3821 tbl 17
6.42 11 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges notes: 1. h = high; l = low; x = dont care; ? = dont know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. 3. device outputs are ensured to be in high-z after the first rising edge of clock upon power-up. read operation with chip enable used (1) notes: 1. h = high; l = low; x = dont care; ? = dont know; z = high impedance. 2. ce = l is defined as ce 1 = l, ce 2 = l and ce 2 = h. ce = h is defined as ce 1 = h, ce 2 = h or ce 2 = l. write operation with chip enable used (1) cycle address r/ w adv/ ld ce (1) cen bw x oe i/o comments n x x l h l x x ? deselected n+1 x x l h l x x ? deselected n+2 a0 h l l l x x z address and control meet setup n+3 x x l h l x x z deselected or stop n+4 a1 h l l l x l q0 address a0 read out. load a1 n+5 x x l h l x x z deselected or stop n+6 x x l h l x l q1 address a1 read out. deselected n+7 a2 h l l l x x z address and control meet setup n+8 x x l h l x x z deselected or stop n+9 x x l h l x l q2 address a2 read out. deselected 3821 tbl 18 cycle address r/ w adv/ ld ce (1) cen bw x oe i/o comments n x x l h l x x ? deselected n+1 x x l h l x x ? deselected n+2 a0 l l l l l x z address and control meet setup n+3 x x l h l x x z deselected or stop n+4 a1 l l l l l x d0 address d0 write in. load a1 n+5 x x l h l x x z deselected or stop n+6 x x l h l x x d1 address d1 write in. deselected n+7 a2 l l l l l x z address and control meet setup n+8 x x l h l x x z deselected or stop n+9 x x l h l x x d2 address d2 write in. deselected 38 21 tb l 19
12 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges symbol parameter test conditions s133 s117 s100 unit com'l ind com'l ind com'l ind i dd operating power supply current device selected, outputs open, adv/ ld = x, v dd = max., v in > v ih or < v il , f = f max (2) 300 310 275 285 250 260 ma i sb1 cmos standby power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = 0 (2) 40 45 40 45 40 45 ma i sb2 clock running power supply current device deselected, outputs open, v dd = max., v in > v hd or < v ld , f = f max (2) 110 120 105 115 100 110 ma i sb3 idle power supply current device selected, outputs open, cen > v ih v dd = max., v in > v hd or < v ld , f = f max (2) 40 45 40 45 40 45 ma 3821 tbl 21 dc electrical characteristics over the opearting temperature and supply voltage range (1) (v dd = 3.3v +/-5%, v hd = v dd ?0.2v, v ld = 0.2v) dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v +/-5%) figure 2. lumped capacitive load, typical derating figure 1. ac test load ac test loads ac test conditions 1 2 3 4 20 30 50 100 200 d tcd (typical, ns) capacitance (pf) 80 5 6 3821 drw 05 , 1.5v 50 w i/o z 0 =50 w 3821 drw 04 + , note: 1. the lbo pin will be internally pulled to v dd if it is not actively driven in the application. symbol parameter test conditions min. max. unit |i li | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i li | lbo input leakage current (1) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current ce > v ih or oe > v ih , v out = 0v tov dd , v dd = max. ___ 5a v ol output low voltage i ol = 5ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = -5ma, v dd = min. 2.4 ___ v 3821 tbl 20 notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc ; f=0 means no input lines are changing. input pulse levels input rise/fall times input timing reference levels output timing reference levels ac test load 0 to 3v 2ns 1.5v 1.5v see figures 1 38 21 tb l 22
6.42 13 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges ac electrical characteristics (v dd = 3.3v +/-5%, commercial and industrial temperature ranges) notes: 1. t f = 1/t cyc . 2. measured as high above 2.0v and low below 0.8v. 3. transition is measured 200mv from steady-state. 4. these parameters are guaranteed with the ac load (figure 1) by device characterization. they are not production tested. 5. to avoid bus contention, the output buffers are designed such that t chz (device turn-off) is about 2 ns faster than t clz (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because t clz is a min. parameter that is worse case at totally different test conditions (0 deg. c, 3.465v) than t chz, which is a max. parameter (worse case at 70 deg. c, 3.135v). symbol parameter 71v546s133 71v546s117 71v546s100 unit min. max. min. max. min. max. clock parameters t cy c clock cycle time 7.5 ____ 8.5 ____ 10 ____ ns t f (1 ) clock frequency ____ 133 ____ 117 ____ 100 mhz t ch (2 ) clock high pulse width 2.5 ____ 3 ____ 3.5 ____ ns t cl (2 ) clock low pulse width 2.5 ____ 3 ____ 3.6 ____ ns output parameters t cd clock high to valid data ____ 4.2 ____ 4.5 ____ 5ns t cdc clock high to data change 1.5 ____ 1.5 ____ 1.5 ____ ns t cl z (3 , 4,5) clock high to output active 1.5 ____ 1.5 ____ 1.5 ____ ns t chz (3 , 4,5) clock high to data high-z 1.5 3.5 1.5 3.5 1.5 3.5 ns t oe output enable access time ____ 4.2 ____ 4.5 ____ 5ns t ol z (3,4) output enable low to data active 0 ____ 0 ____ 0 ____ ns t ohz (3.4) output enab le high to data high-z ____ 3.5 ____ 3.5 ____ 3.5 ns setup times t se clock enable setup time 2.0 ____ 2.0 ____ 2.2 ____ ns t sa address setup time 2.0 ____ 2.0 ____ 2.2 ____ ns t sd data in setup time 1.7 ____ 1.7 ____ 2.0 ____ ns t sw read/write (r/ w ) setup time 2.0 ____ 2.0 ____ 2.2 ____ ns t sadv advance/load (adv/ ld ) setup time 2.0 ____ 2.0 ____ 2.2 ____ ns t sc chip enable/select setup time 2.0 ____ 2.0 ____ 2.2 ____ ns t sb byte write enable ( bw x) setup time 2.0 ____ 2.0 ____ 2.2 ____ ns hold times t he clock enable hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hw read/write (r/ w ) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hadv advance/load (adv/ ld ) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t hb byte write enable ( bw x) hold time 0.5 ____ 0.5 ____ 0.5 ____ ns 3821 tbl 23
14 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges timing waveform of read cycle (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . q (a 2 ) represents the first output from the external address a 2 ; q (a 2+1 ) represents the next output data in the burst sequence of the base address a 2 , etc. where address bits a0 and a1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. ( c e n high, elim inates current l-h clock edge) tc d th a d v p ipeline r ead (b urst w raps around to initial state) tc d c tc lz tc h z tc d tc d c r / w c lk c e n a d v / ld a d d r e s s o e d a t a o ut th e ts e a 1 a 2 o 1(a 1) o 1(a 2) o 1(a 2) tc h tc l tc y c ts a d v th w ts w th a ts a th c ts c b urst p ipeline r ead p ipeline r ead c e 1, c e 2 (2 ) q (a 2+ 1 ) q (a 2+2 ) q (a 2+ 2 ) q (a 2+3 ) 3821 drw 06 b w 1, b w 4
6.42 15 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges timing waveform of write cycles (1,2,3,4,5) notes: 1. d (a 1 ) represents the first input to the external address a 1 . d (a 2 ) represents the first input to the external address a 2 ; d (a 2+1 ) represents the next input data in the burst sequence of the base address a 2 , etc. where address bits a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. burst ends when new address and control are loaded into the sram by sampling adv/ ld low. 4. r/ w is don't care when the sram is bursting (adv/ ld sampled high). the nature of the burst access (read or write) is fixed by the state of the r/ w signal when new address and control are loaded into the sram. 5. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. th e ts e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s o e d a t a in th d ts d tc h tc l tc y c th a d v ts a d v th w ts w th a ts a th c ts c b urst p ipeline w rite p ipeline w rite p ipeline w rite th b ts b (b urst w raps around to initial state) th d ts d ( c e n high, elim inates current l-h clock edge) c e 1, c e 2 (2) d (a 2+ 1 ) d (a 2+ 2 ) d (a 2+ 3 ) d (a 1) d (a 2) d (a 2) 3821 drw 07 b w 1, b w 4 .
16 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges timing waveform of combined read and write cycles (1,2,3) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. th e ts e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s d a t a o ut q (a 3) q (a 1) q (a 6) q (a 7) tc d r ead w rite tc lz tc h z tc h tc l tc y c th w ts w th a ts a a 4 a 3 th c ts c d (a 2) d (a 4) ts d th d tc d c d (a 5) th a d v ts a d v a 6 a 7 a 8 a 5 a 9 r ead w rite r ead d a t a in th b ts b 3821 drw 08 c e 1 , c e 2 (2) b w 1 - b w 4 o e
6.42 17 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges timing waveform of cen operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 2 ) represents the input data to the sram corresponding to address a 2 . 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high.. 3. cen when sampled high on the rising edge of clock will block that l-h transition of the clock from propogating into the sram. the part will behave as if the l-h clock transition did not occur. all internal registers in the sram will retain their previous state. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. th e ts e r / w a 1 a 2 c lk c e n a d v / ld a d d r e s s b w 1 - b w 4 o e d a t a o ut q (a 3) tc d tc lz tc h z tc h tc l tc y c th c ts c d (a 2) ts d th d tc d c a 4 a 5 th a d v ts a d v th w ts w th a ts a a 3 th b ts b d a t a in 3821 drw 09 c e 2 (2 ) q (a 1) b (a 2) c e 1, q (a 1) .
18 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges timing waveform of cs operation (1,2,3,4) notes: 1. q (a 1 ) represents the first output from the external address a 1 . d (a 3 ) represents the input data to the sram corresponding to address a 3 etc. 2. ce 2 timing transitions are identical but inverted to the ce 1 and ce 2 signals. for example, when ce 1 and ce 2 are low on this waveform, ce 2 is high. 3. when either one of the chip enables ( ce 1 , ce 2 , ce 2 ) is sampled inactive at the rising clock edge, a deselect cycle is initiated. the data-bus tri-states two cycles after the in itiation of the deselect cycle. this allows for any pending data transfers (reads or writes) to be completed. 4. individual byte write signals ( bw x) must be valid on all write and burst-write cycles. a write cycle is initiated when r/ w signal is sampled low. the byte write information comes in two cycles before the actual data is presented to the sram. r / w a 1 c lk a d v / ld a d d r e s s o e d a t a o ut q (a 1) tc d tc lz tc h z tc d c tc h tc l tc y c th c ts c ts d th d a 5 a 3 ts b d a t a in th e ts e a 2 th a ts a a 4 th w ts w th b c e n th a d v ts a d v 3821 drw 10 q (a 2) q (a 3) d (a 3) b w 1 - b w 4 c e 1 , c e 2 (2)
6.42 19 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges timing waveform of oe operation (1) note: 1. a read operation is assumed to be in progress. ordering information oe data out tohz tolz toe valid 3821 drw 1 1 plastic thin quad flatpack, 100 pin (pk100-1) s power xx speed pf package pf idt 71v546 133 117 100 clock frequency in megahertz 3821 drw 12 device type part number speed in megahertz t cd parameter clock cycle time 71v546s133pf 71v546s117pf 71v546s100pf 133 mhz 117 mhz 100 mhz 4.2 ns 4.5 ns 5ns 7.5 ns 8.5 ns 10 ns commercial (0c to +70c) industrial (-40c to +85c) x process/ temperature range blank i
20 IDT71V546, 128k x 36, 3.3v synchronous sram with zbt ? ? ? ? ? feature, burst counter and pipelined outputs commercial and industrial temper ature ranges corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408-492-8674 800-544-7726, x4033 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 6/15/99 updated to new format 9/13/99 pg. 12 corrected i sb3 conditions pg. 20 added datasheet document history 12/31/99 pp. 3, 12, 13, 19 added industrial temperature range offerings

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